ARM Cortex-M3 User Manual

Programmer’s Model
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 2-7
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Table 2-2 describes the bit assignments of the IPSR.
Execution PSR
The Execution PSR (EPSR) contains two overlapping fields:
• the Interruptible-Continuable Instruction (ICI) field for interrupted load multiple
and store multiple instructions
• the execution state field for the If-Then (IT) instruction, and the Thumb state bit
(T-bit).
Interruptible-continuable instruction field
Load Multiple (LDM) operations and Store Multiple (STM) operations are interruptible.
The ICI field of the EPSR holds the information required to continue the load or store
multiple from the point that the interrupt occurred.
If-then state field
The IT field of the EPSR contain the execution state bits for the If-Then instruction.
Table 2-2 Interrupt Program Status Register bit assignments
Field Name Definition
[31:9] - Reserved.
[8:0] ISR NUMBER Number of pre-empted exception.
Base level = 0
NMI = 2
SVCall = 11
INTISR[0] = 16
INTISR[1] = 17
.
.
.
INTISR[15] = 31
.
.
.
INTISR[239] = 255

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit