ARM Cortex-M3 User Manual

Introduction
1-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
1.3 Execution pipeline stages
The following stages make up the pipeline:
• the Fetch stage
• the Decode stage
• the Execute stage.
Figure 1-2 shows the pipeline stages of the processor, and the pipeline operations that
take place at each stage.
Figure 1-2 Cortex-M3 pipeline stages
Fetch
Instruction
Decode
and
Register
Read
Fe
Address
generation
unit
Branch
Shift
ALU
and
Branch
Address
phase
and
writeback
Data
phase
Load/
Store
and
Branch
WR
Multiply
and
Divide
De
Ex
LSU branch
result
ALU branch not forwarded/speculated
LSU branch result
Branch forwarding
and speculation

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit