ARM Cortex-M3 User Manual

Signal Descriptions
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. A-17
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A.14 Test interface
Table A-14 lists the signals of the test interface.
Table A-14 Test interface
Name Direction Description
SE Input Scan enable.
RSTBYPASS Input Reset bypass for scan testing. PORESETn is the only reset used during scan testing.
CGBYPASS Input Architectural clock gate bypass for scan testing.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit