ARM Cortex-M3 User Manual

System Debug
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Figure 11-18 ITM Lock Status Register bit assignments
Table 11-27 describes the bit assignments of the ITM Lock Status Register
31
0
1
Reserved
Present
23
ByteAcc
Access
Table 11-27 ITM Lock Status Register bit assignments
Bits Field Function
[31:3] - Reserved.
[2] ByteAcc You cannot implement 8-bit lock accesses.
[1] Access Write access to component is blocked. All writes are ignored, reads are permitted.
[0] Present Indicates that a lock mechanism exists for this component.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit