ARM Cortex-M3 User Manual

Trace Port Interface Unit
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 17-7
APB interface
Table 17-4 describes the APB interface inputs.
SWOACTIVE Output SWO mode selected. Use for pin multiplexing.
TPIUACTIV Output Indicates that the TPIU has data that is in the process of being output.
TPIUBAUD Output Toggles at baud frequency (in TRACECLKIN domain).
Table 17-3 Miscellaneous configuration inputs (continued)
Name Type Description
Table 17-4 APB interface
Name Type Description
PSEL Input Peripheral select
PWRITE Input Peripheral write control
PENABLE Input Peripheral transfer enable
PADDR[11:2] Input Peripheral address
PWDATA[31:0] - Write data
PRDATA[31:0] - Read data

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit