ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
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Bus Fault Status Register
The flags in the Bus Fault Status Register indicate the cause of bus access faults.
The register address, access type, and Reset state are:
Address
0xE000ED29
Access Read/write-one-to-clear
Reset state
0x00000000
Figure 8-18 shows the bit assignments of the Bus Fault Status Register.
Figure 8-18 Bus Fault Status Register bit assignments
[2] - Reserved
[1] DACCVIOL Data access violation flag. Attempting to load or store at a location that does not permit the
operation sets the DACCVIOL flag. The return PC points to the faulting instruction. This error
loads MMAR with the address of the attempted access.
[0] IACCVIOL Instruction access violation flag. Attempting to fetch an instruction from a location that does
not permit execution sets the IACCVIOL flag. This occurs on any access to an XN region, even
when the MPU is disabled or not present. The return PC points to the faulting instruction. The
MMAR is not written.
Table 8-22 Memory Manage Fault Status Register bit assignments (continued)
Bits Field Function
76543210
BFARVALID
STKERR
UNSTKERR
IMPRECISERR
PRECISERR
IBUSERR
Reserved

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit