ARM Cortex-M3 User Manual

Embedded Trace Macrocell
14-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Figure 14-3 shows the full branch with exception packet.
Figure 14-3 Exception encoding for branch packet
2 bytes exception Reserved 7 22
2 bytes exception Reserved 13 23
2 bytes exception IRQ8 24 24
2 bytes exception IRQ9 25 25
2 bytes exception IRQ10 26 26
....
....
....
2 bytes exception IRQ239 255 255
Table 14-8 Exception tracing mapping (continued)
Number of bytes Exception ETMINTNUM Traced value
Address byte 0
Address byte 1
(optional)
Address byte 2
(optional)
Address byte 3
(optional)
Address byte 4
(optional)
Exception information
Byte 0
Exception information
Byte 1 (optional)
01234
5
67
C
C
C
C
C
C
C
1
NS
E/
Addr[13]
E/
Addr[20]
E/
Addr[27]
E
0
T2EE
SBZ
Canc
0 1
Addr[6:1]
Addr[12:7]
Addr[19:14]
Addr[26:21]
Addr[31:28]
Excp[3:0]
Excp[8:4]

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit