ARM Cortex-M3 User Manual

Embedded Trace Macrocell
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-15
Unrestricted Access Non-Confidential
The final address byte uses bits [7:6] set to 0b01 to indicate the end of the address field.
Exception data follows this field. Exception byte 0 sets bit [7] to 1 if a second exception
byte follows. If there is no exception present, and only address bits [6:1] change, then a
single byte is used. If an exception is present, then at least two bytes signal the address.
When turning off trace immediately before entry to an exception handler, the ETM
remains enabled until the exception is taken. This enables it to trace the branch address,
exception type and resume information.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit