ARM Cortex-M3 User Manual

AHB Trace Macrocell Interface
16-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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16.1 About the AHB trace macrocell interface
The AHB Trace Macrocell (HTM) interface enables a simple connection of the AHB
trace macrocell to the processor. It provides a channel for the data trace to the HTM.
To use the HTM interface, the trace level must be set to level 3 before implementation.
TRCENA must also be set to 1 before you enable the HTM to enable the HTM port to
supply trace data.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit