ARM Cortex-M3 User Manual

Introduction
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 1-11
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Chapter 13 Debug Port describes the SW/SWJ-DP.
1.2.14 Interrupts
You can configure the number of external interrupts at implementation from 1 to 240.
You can configure the number of bits of interrupt priority at implementation from three
to eight bits.
1.2.15 Observation
You can configure the system at implementation time to enable the observation of some
internal signals. These include the register bank ports and the instruction in the execute
stage of the pipeline.
1.2.16 ROM table
The ROM table is modified from that described in ROM memory table on page 4-7 if:
• additional debug components have been added into the system
• all debug functionality has been removed from the implementation.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit