ARM Cortex-M3 User Manual

Memory Map
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 4-3
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Table 4-1 shows the processor interfaces that are addressed by the different memory
map regions
Table 4-1 Memory interfaces
Memory Map Interface
Code Instruction fetches are performed over the ICode bus. Data accesses are performed over the
DCode bus.
SRAM Instruction fetches and data accesses are performed over the system bus.
SRAM_bitband Alias region. Data accesses are aliases. Instruction accesses are not aliases.
Peripheral Instruction fetches and data accesses are performed over the system bus.
Periph_bitband Alias region. Data accesses are aliases. Instruction accesses are not aliases.
External RAM Instruction fetches and data accesses are performed over the system bus.
External Device Instruction fetches and data accesses are performed over the system bus.
Private Peripheral Bus Accesses to:
• Instrumentation Trace Macrocell (ITM)
• Nested Vectored Interrupt Controller (NVIC)
• Flashpatch and Breakpoint (FPB)
• Data Watchpoint and Trace (DWT)
• Memory Protection Unit (MPU)
are performed to the processor internal Private Peripheral Bus (PPB).
Accesses to:
• Trace Point Interface Unit (TPIU)
• Embedded Trace Macrocell (ETM)
• System areas of the PPB memory map
are performed over the external PPB interface.
This memory region is Execute Never (XN), and so instruction fetches are prohibited. An MPU,
if present, cannot change this.
System System segment for vendor system peripherals. This memory region is XN, and so instruction
fetches are prohibited. An MPU, if present, cannot change this.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit