AC Characteristics
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 19-5
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Table 19-7 shows the timing parameters for the test input ports.
Table 19-8 shows the timing parameters for the Embedded Trace Macrocell (ETM).
Table 19-9 shows the timing parameters for the miscellaneous output ports.
Table 19-7 Test input ports timing parameters
Input delay Min. Input delay Max. Signal name
Clock uncertainty 10% SE
Clock uncertainty 10% SI
Clock uncertainty 10% RSTBYPASS
Clock uncertainty 10% CGBYPASS
Clock uncertainty 10% WSII
Clock uncertainty 10% WSOI
Table 19-8 ETM input port timing parameters
Input delay Min. Input delay Max. Signal name
Clock uncertainty 30% ETMPWRUP
Clock uncertainty 50% ETMFIFOFILL
Table 19-9 Miscellaneous output ports timing parameters
Output delay Min. Output delay Max. Signal name
Clock uncertainty 50% LOCKUP
Clock uncertainty 50% SYSRESETREQ
Clock uncertainty 50% BRCHSTAT[3:0]
Clock uncertainty 50% HALTED
Clock uncertainty 50% TXEV
Clock uncertainty 50% ATIDITM[6:0]
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