ARM Cortex-M3 User Manual

Embedded Trace Macrocell
14-22 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Power Down Status Register
The Power Down Status Register (PDSR) indicates whether the ETM is powered up or
not.
Reset value:
0x00000001
Only bit [0] is implemented. It indicates whether the ETM debug power domain is
powered up or not:
• 0 = ETM debug power domain not powered up
• 1 = ETM debug power domain powered up.
Note
If the ETM is not powered up, the ETM registers are not accessible.
14.6.4 ETM Event resources
The trace enable event and trigger event are configured using the same mechanism. For
each event, two resources are defined, together with a boolean function of those two
resources. Table 14-10 and Table 14-11 on page 14-23 show these.
Table 14-10 Boolean function encoding for events
Encoding Function
b000 A
b001 NOT(A)
b010 A AND B
b011 NOT(A) AND B
b100 NOT(A) AND NOT (B)
b101 A OR B
b110 NOT (A) OR B
b111 NOT (A) OR NOT (B)

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit