Embedded Trace Macrocell
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• Advanced Peripheral Bus (APB) interface signals. See Table 14-6 on page 14-6.
Table 14-1 ETM core interface inputs and outputs
Name Description Qualified by Direction
ETMIA[31:1] Core instruction address bus. ETMIVALID Input
ETMIVALID Current instruction data represents an instruction. - Input
ETMDVALID Current instruction data represents an instruction. - Input
ETMICCFAIL Instruction failed its condition code. ETMIVALID Input
ETMIBRANCH Instruction is a branch target. ETMIVALID Input
ETMIINDBR Instruction is an indirect branch target. ETMIBRANCH Input
ETMFLUSH PC modified before next instruction. - Input
ETMISTALL Indicates that the last instruction signalled by the core has not
yet entered execute.
- Input
ETMFINDBR PC modified by an indirect operation. ETMFLUSH Input
ETMINTSTAT[2:0] Exception entry and exit. - Input
ETMINTNUM[8:0] Exception type. ETMINTSTAT Input
ETMCANCEL Exception is a canceling exception. ETMINTSTAT Input
COREHALT Core is halted. - Input
DWTMATCH [3:0] Indicates that the Data Watchpoint and Trace (DWT) trigger
units have matched the conditions currently present on the
address, data and control buses.
- Input
DWTINOTD[3:0] Indicates that the DWT trigger units are performing
comparisons on PC value (set) or data address (clear).
- Input
Table 14-2 Miscellaneous configuration inputs
Name Description Direction Clock domain
NIDEN Non invasive debug enable Input FCLK
EXTIN[1:0] External input resource Input FCLK
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