ARM Cortex-M3 User Manual

System Debug
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-3
Unrestricted Access Non-Confidential
11.2 System debug access
Debug control and data access occurs through the Advanced High-performance
Bus-Access Port (AHB-AP) interface. This interface is driven by either the Serial Wire
Debug Port (SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP) components. See
Chapter 13 Debug Port for information on the SW-DP and SWJ-DP components.
Access includes:
• The internal PPB. Through this bus, the debugger can access components,
including:
— Nested Vectored Interrupt Controller (NVIC). Debug access to the
processor core is made through the NVIC. For details, see Chapter 10 Core
Debug.
—DWT unit.
— FPB unit.
—ITM.
— Memory Protection Unit (MPU).
Note
During a system reset the debugger can read all registers within the PPB space. It
can also write to registers within the PPB space that are only reset by a power on
reset.
• The External Private Peripheral Bus. Through this bus, debug can access:
— ETM. A low-cost trace macrocell that supports instruction trace only. See
Chapter 14 Embedded Trace Macrocell for more information.
— Trace Port Interface Unit (TPIU). This component acts as a bridge between
the Cortex-M3 trace data (from the ITM, and ETM if present) and an
off-chip Trace Port Analyzer. See Chapter 17 Trace Port Interface Unit for
more information.
—ROM table.
• The DCode bus. Through this bus, debug can access memory located in code
space.
• The System bus. Provides access to bus, memory, and peripherals located in
system bus space.
Figure 11-1 on page 11-4 shows the structure of the system debug access, and shows
how the AHB-AP can access each of the system components and external buses.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit