ARM Cortex-M3 User Manual

Signal Descriptions
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. A-7
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A.5 Low power interface
Table A-5 lists the signals of the low power interface.
Table A-5 Low power interface signals
Name Direction Description
SLEEPDEEP Output Indicates that the Cortex-M3 clock can be stopped.
SLEEPING Output Indicates that the Cortex-M3 clock can be stopped.
SLEEPHOLDACKn Output Acknowledge signal for SLEEPHOLDREQn.
WICMASKISR Output WIC Active high set of signals indicating which interrupts would cause wakeup.
WICMASKMON Output WIC Active high signal indicating that debug monitor would cause wakeup.
WICMASKNMI Output WIC Active high signal indicating that NMI would cause wakeup.
WICMASKRXEV Output WIC Active high signal indicating that RXEV would cause wakeup.
WICLOAD Output Causes WIC to be loaded with sensitivity data given by WICMASK*.
WICCLEAR Output Causes WIC to clear registered sensitivity data.
WICDSACKn Output Active low indication that accepts WICDSREQn and means that SLEEPDEEP
is WIC mode sleep.
SLEEPHOLDREQn Input Request to extend sleep. Can only be asserted when SLEEPING is high.
WICDSREQn Input WIC Active low request from WIC that SLEEPDEEP be WIC mode sleep.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit