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Introduction

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1.1 About the processor

The processor is a low-power processor that features low gate count, low interrupt

latency, and low-cost debug. It is intended for deeply embedded applications that

require fast interrupt response features. The processor implements the ARMv7-M

architecture.

The processor incorporates:

• Processor core. A low gate count core, with low latency interrupt processing that

features:

— A Thumb instruction set subset, defined in the ARMv7-M Architecture

Reference Manual.

—Banked Stack Pointer (SP) only.

— Hardware divide instructions, SDIV and UDIV (Thumb 32-bit

instructions).

— Handler and Thread modes.

— Thumb and Debug states.

— Interruptible-continued LDM/STM, PUSH/POP for low interrupt latency.

— Automatic processor state saving and restoration for low latency Interrupt

Service Routine (ISR) entry and exit.

— Support for ARMv6 BE8 or LE accesses.

— Support for ARMv6 unaligned accesses.

• Nested Vectored Interrupt Controller (NVIC) closely integrated with the

processor core to achieve low latency interrupt processing. Features include:

— External interrupts of 1 to 240 configurable size.

— Bits of priority of 3 to 8 configurable size.

— Dynamic reprioritization of interrupts.

— Priority grouping. This enables selection of pre-empting interrupt levels

and non pre-empting interrupt levels.

— Support for tail-chaining and late arrival of interrupts. This enables

back-to-back interrupt processing without the overhead of state saving and

restoration between interrupts.

— Processor state automatically saved on interrupt entry, and restored on

interrupt exit, with no instruction overhead.

• Memory Protection Unit (MPU). An optional MPU for memory protection:

— Eight memory regions.

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit