ARM Cortex-M3 User Manual

ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. v
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Contents
Cortex-M3 Technical Reference Manual
Preface
About this book ............................................................................................. xx
Feedback .................................................................................................... xxv
Chapter 1 Introduction
1.1 About the processor .................................................................................... 1-2
1.2 Components, hierarchy, and implementation .............................................. 1-4
1.3 Execution pipeline stages ......................................................................... 1-12
1.4 Prefetch Unit ............................................................................................. 1-14
1.5 Branch target forwarding ........................................................................... 1-15
1.6 Store buffers ............................................................................................. 1-18
1.7 Product revisions ...................................................................................... 1-19
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 Privileged access and user access ............................................................. 2-3
2.3 Registers ..................................................................................................... 2-4
2.4 Data types ................................................................................................. 2-10
2.5 Memory formats ........................................................................................ 2-11
2.6 Instruction set summary ............................................................................ 2-13

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit