Contents
vi Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Chapter 3 System Control
3.1 Summary of processor registers ................................................................. 3-2
Chapter 4 Memory Map
4.1 About the memory map .............................................................................. 4-2
4.2 Bit-banding ................................................................................................. 4-5
4.3 ROM memory table .................................................................................... 4-7
Chapter 5 Exceptions
5.1 About the exception model ......................................................................... 5-2
5.2 Exception types .......................................................................................... 5-4
5.3 Exception priority ........................................................................................ 5-6
5.4 Privilege and stacks .................................................................................... 5-9
5.5 Pre-emption .............................................................................................. 5-11
5.6 Tail-chaining ............................................................................................. 5-14
5.7 Late-arriving .............................................................................................. 5-15
5.8 Exit ............................................................................................................ 5-17
5.9 Resets ...................................................................................................... 5-20
5.10 Exception control transfer ......................................................................... 5-24
5.11 Setting up multiple stacks ......................................................................... 5-25
5.12 Abort model .............................................................................................. 5-27
5.13 Activation levels ........................................................................................ 5-32
5.14 Flowcharts ................................................................................................ 5-34
Chapter 6 Clocking and Resets
6.1 Clocking ...................................................................................................... 6-2
6.2 Resets ........................................................................................................ 6-4
6.3 Cortex-M3 reset modes .............................................................................. 6-5
Chapter 7 Power Management
7.1 About power management ......................................................................... 7-2
7.2 System power management ....................................................................... 7-3
Chapter 8 Nested Vectored Interrupt Controller
8.1 About the NVIC ........................................................................................... 8-2
8.2 NVIC programmer’s model ......................................................................... 8-3
8.3 Level versus pulse interrupts .................................................................... 8-43
Chapter 9 Memory Protection Unit
9.1 About the MPU ........................................................................................... 9-2
9.2 MPU programmer’s model .......................................................................... 9-3
9.3 MPU access permissions ......................................................................... 9-13
9.4 MPU aborts ............................................................................................... 9-15
9.5 Updating an MPU region .......................................................................... 9-16
9.6 Interrupts and updating the MPU .............................................................. 9-19
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