ARM Cortex-M3 User Manual

Embedded Trace Macrocell
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-7
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14.2 Data tracing
The Cortex-M3 system can perform low-bandwidth data tracing using the Data
Watchpoint and Trace (DWT) and Instruction Trace Macrocell (ITM) components. To
enable support of instruction trace with a low pin-count, data trace is not included in the
ETM. This considerably reduces gate count for the ETM, because the triggering
resources are simplified.
When the ETM is implemented in the processor, the two trace sources, ITM and ETM,
both feed into the TPIU, where they are combined and usually output over the trace port.
DWT is able to provide either focused data trace, or global data trace, subject to FIFO
overflow issues. The TPIU is optimized for the requirements of a single core Cortex-M3
system.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit