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Exceptions

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5.5 Pre-emption

The following sections describe the behavior of the processor when it takes an

exception:

• Stacking

• Late-arriving on page 5-15

• Tail-chaining on page 5-14.

5.5.1 Stacking

When the processor invokes an exception, it automatically stores the following eight

registers to the SP in the following order:

• Program Counter (PC)

• Processor Status Register (xPSR)

•r0-r3

•r12

• Link Register (LR).

The SP is decremented by eight words by the completion of the stack push. Figure 5-1

shows the contents of the stack after an exception pre-empts the current program flow.

Figure 5-1 Stack contents after pre-emption

Note

• Figure 5-1 shows the order on the stack.

• If STKALIGN is set in the Configuration Control Register then an extra word can

be inserted before the stacking takes place. See Configuration Control Register on

page 8-26.

After returning from the ISR, the processor automatically pops the eight registers from

the stack. Interrupt return is passed as a data field in the LR, so ISR functions can be

normal C/C++ functions, and do not require a veneer.

Old SP

xPSR

r12

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit