ARM Cortex-M3 User Manual

Core Debug
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 10-9
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Figure 10-3 Debug Exception and Monitor Control Register bit assignments
Table 10-4 shows the bit functions of the Debug Exception and Monitor Control
Register.
SBZPSBZPSBZP SBZP
31 10
TRCENA
34567891011151617181920232425
MON_REQ VC_HARDERR
MON_STEP
MON_EN
MON_PEND
VC_INTERR
VC_BUSERR
VC_STATERR
VC_CHKERR
VC_NOCPERR
VC_MMERR
VC_CORERESET
Table 10-4 Debug Exception and Monitor Control Register
Bits Type Field Function
[31:25] - - Reserved, SBZP
[24] Read/write TRCENA This bit must be set to 1 to enable use of the trace and debug blocks:
• Data Watchpoint and Trace (DWT)
• Instrumentation Trace Macrocell (ITM)
• Embedded Trace Macrocell (ETM)
• Trace Port Interface Unit (TPIU).
This enables control of power usage unless tracing is required. The
application can enable this, for ITM use, or use by a debugger.
Note
If no debug or trace components are present in the implementation then
it is not possible to set TRCENA.
[23:20] - - Reserved, SBZP
[19] Read/write
MON_REQ
a
This enables the monitor to identify how it wakes up:
1 = woken up by MON_PEND
0 = woken up by debug exception.
[18] Read/write
MON_STEP
a
When MON_EN = 1, this steps the core. When MON_EN = 0, this bit
is ignored. This is the equivalent to C_STEP. Interrupts are only
stepped according to the priority of the monitor and settings of
PRIMASK, FAULTMASK, or BASEPRI.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit