ARM Cortex-M3 User Manual

Bus Interface
12-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
12.11 Write buffer
To prevent bus wait cycles from stalling the processor during data stores, buffered stores
to the DCode and System buses go through a one-entry write buffer. If the write buffer
is full, subsequent accesses to the bus stall until the write buffer has drained. The write
buffer is only used if the bus waits the data phase of the buffered store, otherwise the
transaction completes on the bus.
DMB and DSB instructions wait for the write buffer to drain before completing. If an
interrupt comes in while DMB/DSB is waiting for the write buffer to drain, the opcode
after the DMB/DSB is returned to on the completion of the interrupt. This is because
interrupt processing is a memory barrier operation.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit