ARM Cortex-M3 User Manual

Memory Map
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 4-7
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4.3 ROM memory table
Table 4-3 describes the ROM memory.
Table 4-3 ROM table
Offset Value Name Description
0x000 0xFFF0F003 NVIC Points to the NVIC at 0xE000E000 .
0x004 0xFFF02002 or 003 if present DWT Points to the Data Watchpoint and Trace block at 0xE0001000 .
Value has bit [0] set if DWT is present.
0x008 0xFFF03002 or 003 if present FPB Points to the Flash Patch and Breakpoint block at 0xE0002000 .
Value has bit [0] set to 1 if FPB is present.
0x00C 0xFFF01002 or 003 if present ITM Points to the Instrumentation Trace block at 0xE0000000 . Value
has bit [0] set if ITM is present.
0x010 0xFFF41002 or 003 if present TPIU Points to the TPIU. Value has bit [0] set to 1 if TPIU is present.
TPIU is at 0xE0040000 .
0x014 0xFFF42002 or 003 if present ETM Points to the ETM. Value has bit [0] set to 1 if ETM is present.
ETM is at 0xE0041000 .
0x018 0 End Marks the end of the ROM table. If CoreSight components are
added, they are added starting from this location and the End
marker is moved to the next location after the additional
components.
0xFCC 0x1 MEMTYPE Bits [31:1] RAZ. Bit [0] is set when the system memory map is
accessible using the DAP. Bit [0] is clear when only debug
resources are accessible using the DAP.
0xFD0 0x0 PID4 -
0xFD4 0x0 PID5 -
0xFD8 0x0 PID6 -
0xFDC 0x0 PID7 -
0xFE0 0x0 PID0 -
0xFE4 0x0 PID1 -
0xFE8 0x0 PID2 -
0xFEC 0x0 PID3 -
0xFF0 0x0D CID0 -

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit