ARM Cortex-M3 User Manual

Embedded Trace Macrocell Interface
15-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Note
• The encoding b1000 is only asserted in the cycle after conditional decode
branches if the branch is taken. This is a registered output, so could be used to
drive a multiplexor of addresses in the memory controller.
• Multicycle LSU in the b0101 encoding suppresses fetches during execute because
it is known that the unconditional branch is executed so sequential fetches are
prevented.
• Encodings are present for the multicycle duration of the decode, not only when
decode enable is asserted.
Speculative fetches might be cancelled during wait states. This means that the fetch
address might change to a new address while HREADY is low. See AMBA 3
compliance on page 12-3.
Figure 15-1 and Figure 15-2 on page 15-9 show a conditional branch backwards not
taken and taken. The branch occurs speculatively in the decode phase of the opcode.
The branch target is a halfword unaligned 16-bit opcode.
Figure 15-1 Conditional branch backwards not taken
POP {PC} 16 bits Execute -
POP {PC} 32 bits Execute -
TBB/TBH 32 bits Execute -
Table 15-3 Branches and stages evaluated by the processor (continued)
Branch Instruction Instruction size Stage branch target is issued Notes
ETMIVALID
ETMCCFAIL
ETMIA
BRCHSTAT
HTRANSI
HADDRI
HCLK
0x1000 0x1002
0001
NONSEQ
Fetch ahead of 0x1004+
0x0FF0
0000 0000

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit