ARM Cortex-M3 User Manual

Memory Protection Unit
9-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Non-Confidential
Unrestricted Access
For information about access permission, see MPU access permissions on page 9-13.
[16] B Bufferable bit:
1 = bufferable
0 = not bufferable.
[15:8] SRD Sub-Region Disable (SRD) field. Setting an SRD bit disables the corresponding sub-region.
Regions are split into eight equal-sized sub-regions. Sub-regions are not supported for region sizes
of 128 bytes and less. For more information, see Sub-Regions on page 9-12.
[7:6] - Reserved.
[5:1] SIZE MPU Protection Region Size Field. See Table 9-7.
[0] ENABLE Region enable bit.
Table 9-6 MPU Region Attribute and Size Register bit assignments (continued)
Bits Field Function
Table 9-7 MPU protection region size field
Region Size
b00000 Reserved
b00001 Reserved
b00010 Reserved
b00011 Reserved
b00100 32B
b00101 64B
b00110 128B
b00111 256B
b01000 512B
b01001 1KB
b01010 2KB
b01011 4KB
b01100 8KB
b01101 16KB

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit