ARM Cortex-M3 User Manual

AC Characteristics
19-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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19.1 Processor timing parameters
This section describes the input and output port timing parameters for the processor.
The maximum timing parameter or constraint delay for each processor signal applied to
the SoC is given as a percentage in Table 19-1 to Table 19-16 on page 19-10. The input
and output delay columns provide the maximum and minimum time as a percentage of
the processor clock cycle given to the SoC for that signal.
19.1.1 Input and output port timing parameters
Table 19-1 shows the timing parameters for the miscellaneous input ports.
Table 19-2 shows the timing parameters for the low power input ports.
Table 19-1 Miscellaneous input ports timing parameters
Input delay Min. Input delay Max. Signal name
Clock uncertainty 10% PORESETn
Clock uncertainty 10% SYSRESETn
Clock uncertainty 50% BIGEND
Clock uncertainty 50% EDBGRQ
Clock uncertainty 50% STCLK
Clock uncertainty 50% STCALIB[25:0]
Clock uncertainty 50% RXEV
Clock uncertainty 50% AUXFAULT[31:0]
Clock uncertainty 10% IFLUSH
Clock uncertainty 50% PPBLOCK[5:0]
Table 19-2 Low power input ports timing parameters
Input delay Min. Input delay Max. Signal name
Clock uncertainty 50% SLEEPHOLDREQn
Clock uncertainty 50% WICDSREQn

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit