ARM Cortex-M3 User Manual

Introduction
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 1-19
Unrestricted Access Non-Confidential
1.7 Product revisions
This section summarizes the differences in functionality between the different releases
of this processor:
• Differences in functionality between r0p0 and r1p0
• Differences in functionality between r1p0 and r1p1 on page 1-20
• Differences in functionality between r1p1 and r2p0 on page 1-20.
1.7.1 Differences in functionality between r0p0 and r1p0
In summary, the differences in functionality include:
• Addition of configurable data value comparison to the DWT module. See DWT
on page 11-13.
• Addition of a MATCHED bit to DWT_FUNCTION. See DWT on page 11-13.
• Addition of ETMFIFOFULL as an input to Cortex-M3. See ETM interface on
page A-14.
• Addition of ETMISTALL as an output to Cortex-M3. See ETM interface on
page A-14.
• Addition of SWVMode to the ITM. To support SWVMode, TPIUACTV and
TPIUBAUD have been added as outputs from the TPIU and are inputs to the
processor. See ITM on page 11-30.
• CPUID Base Register VARIANT field changed to indicate Rev1. See NVIC
register descriptions on page 8-7.
• Cortex-M3 Rev0 Bit-band accesses in BE8 mode required access sizes to be byte.
Cortex-M3 Rev1 has been changed so that BE8 bit-band accesses function with
any access size.
• Addition of a configuration bit called STKALIGN to ensure that all exceptions
have eight-byte stack alignment. See NVIC register descriptions on page 8-7.
• Addition of the Auxiliary Fault Status Register at address
0xE000ED3C . To set this
register, a 32-bit input bus called AUXFAULT has been added. See NVIC register
descriptions on page 8-7.
• Addition of HTM support. See Chapter 16 AHB Trace Macrocell Interface.
• ICode and DCode cacheable and bufferable HPROT values permanently tied to
write-through. See ICode bus interface on page 12-4 and DCode bus interface on
page 12-6.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit