ARM Cortex-M3 User Manual

Exceptions
5-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Table 5-4 describes the steps that the processor takes before it enters an ISR.
Figure 5-2 on page 5-13 shows an example of exception entry timing.
Table 5-4 Exception entry steps
Action Restartable? Description
Push eight registers
a
No. Pushes xPSR, PC, r0, r1, r2, r3, r12, and LR on selected stack.
Read vector table Yes. Late-arriving
exception can cause
restart.
Reads vector table from memory based on
table base + (exception number 4). Read on the ICode bus can
be done simultaneously with register pushes on the DCode bus.
Read SP from vector table No. On Reset only, updates SP to top of stack from vector table.
Other exceptions do not modify SP except to select stack, push,
and pop.
Update PC No. Updates PC with vector table read location. Late-arriving
exceptions cannot be processed until the first instruction starts to
execute.
Load pipeline Yes. Pre-emption
reloads pipeline from
new vector table read.
Loads instructions from location pointed to by vector table. This
is done in parallel with register push.
Update LR No. LR is set to EXC_RETURN to exit from exception.
EXC_RETURN is one of 16 values as defined in ARMv7-M
Architecture Reference Manual.
a. When tail-chaining, this step is skipped.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit