ARM Cortex-M3 User Manual

Embedded Trace Macrocell
14-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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14.1 About the ETM
The ETM is an optional debug component that enables reconstruction of program
execution. The ETM is designed to be a high-speed, low-power debug tool that only
supports instruction trace. This ensures that area is minimized, and that gate count is
reduced.
14.1.1 ETM block diagram
Figure 14-1 on page 14-3 shows a block diagram of the ETM, and shows how the ETM
interfaces to the Trace Port Interface Unit (TPIU).

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit