ARM Cortex-M3 User Manual

Exceptions
5-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Table 5-3 shows how writing to PRIGROUP splits an eight bit PRI_N field into a
pre-emption priority field (x) and a subpriority field (y).
Note
• Table 5-3 shows the priorities for the processor configured with eight bits of
priority.
• For a processor configured with less than eight bits of priority, the lower bits of
the register are always 0. For example, if four bits of priority are implemented,
PRI_N[7:4] sets the priority, and PRI_N[3:0] is 4'b0000.
An interrupt can pre-empt another interrupt in progress only if its pre-emption priority
is higher than that of the interrupt in progress.
For more information on priority optimizations, priority level grouping, and priority
masking, see the ARMv7-M Architecture Reference Manual.
Table 5-3 Priority grouping
Interrupt priority level field, PRI_N[7:0]
PRIGROUP[2:0]
Binary point
position Pre-emption field Subpriority field
Number of
pre-emption
priorities
Number of
subpriorities
b000 bxxxxxxx.y [7:1] [0] 128 2
b001 bxxxxxx.yy [7:2] [1:0] 64 4
b010 bxxxxx.yyy [7:3] [2:0] 32 8
b011 bxxxx.yyyy [7:4] [3:0] 16 16
b100 bxxx.yyyyy [7:5] [4:0] 8 32
b101 bxx.yyyyyy [7:6] [5:0] 4 64
b110 bx.yyyyyyy [7] [6:0] 2 128
b111 b.yyyyyyyy None [7:0] 0 256

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit