ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
8-16 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Note
Writing to the Interrupt Clear-Pending Register has no effect on an interrupt that is
active unless it is also pending.
The register address, access type, and Reset state are:
Address
0xE000E280 - 0xE000E29C
Access Read/write
Reset state
0x00000000
Table 8-11 describes the field of the Interrupt Clear-Pending Registers.
Active Bit Register
Read the Active Bit Register to determine which interrupts are active. Each flag in the
register corresponds to one of the 32 interrupts.
The register address, access type, and Reset state are:
Address
0xE000E300 - 0xE00031C
Access Read-only
Reset state
0x00000000
Table 8-12 describes the field of the Active Bit Register.
Table 8-11 Interrupt Clear-Pending Registers bit assignments
Bits Field Function
[31:0] CLRPEND Interrupt clear-pending bits:
1 = clear pending interrupt
0 = do not clear pending interrupt.
Writing 0 to a CLRPEND bit has no effect. Reading the bit returns its current state.
Table 8-12 Active Bit Register bit assignments
Bits Field Function
[31:0] ACTIVE Interrupt active flags:
1 = interrupt active or pre-empted and stacked
0 = interrupt not active or stacked.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit