ARM Cortex-M3 User Manual

Signal Descriptions
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A.10 ITM interface
Table A-10 lists the signals of the ITM interface.
Table A-10 ITM interface
Name Direction Description
ATVAL ID Output ATB valid.
AFREADY Output ATB flush.
ATDATA[7:0] Output ATB data.
ATIDITM[6:0] Output ITM ID for TPIU.
ATREADY Input ATB ready.
TPIUACTV Input TPIU active indication signal.
TPIUBAUD Input Reference for the timestamp counter, so that timestamps are at the observable baud rate
of the external protocol.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit