ARM Cortex-M3 User Manual

Revisions
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. B-5
Unrestricted Access Non-Confidential
Addition of note about configuring TPIU registers to be
present or not
Summary of the TPIU registers on page 17-8
The following TPIU registers removed from summary table
and descriptions:
• Trigger control registers
• EXTCTL port registers
• Test pattern registers
Table 17-5 on page 17-8 and Description of the TPIU
registers on page 17-9
The following TPIU registers added to the summary table
and descriptions:
• Integration Register: TRIGGER
• Integration Mode Control Register
• Integration Register: FIFO data 0
• Integration Register: FIFO data 1
• Claim tag set register
• Claim tag clear register
• Device ID register
• PID registers
• CID registers
Table B-2 Differences between issue F and issue G
Change Location
Wake-up Interrupt Controller (WIC) added to Cortex-M3 block
diagram
Figure 1-1 on page 1-5
Section 1-2 and section 1-3 combined Components, hierarchy, and implementation on
page 1-4
New subsection added to list changes in functionality between
r1p1 and r2p0
Differences in functionality between r1p1 and r2p0
on page 1-20
New subsection added to describe the WIC WIC on page 1-10
New bullet point to describe FIXHMASTERTYPE pin Differences in functionality between r1p1 and r2p0
on page 1-20
Table of supported instruction removed Chapter 2 Programmer’s Model
Table B-1 Differences between issue E and issue F (continued)
Change Location

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit