ARM Cortex-M3 User Manual

Trace Port Interface Unit
17-6 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Advanced Trace Bus interface
There is one or two ATB interfaces depending on the TPIU configuration. Table 17-2
describes the ATB port signals. The signals for port 2 are not used when the TPIU is
configured with a single ATB interface.
Miscellaneous configuration inputs
Table 17-3 describes the miscellaneous configuration inputs.
Table 17-2 ATB port signals
Name Type Description
CLK Input Trace bus and APB interface clock.
nRESET Input Reset for the CLK domain (ATB/APB interface).
CLKEN Input Clock enable for CLK domain.
ATVAL ID 1S Input Data from trace source 1 is valid in this cycle.
ATREADY1S Output If this signal is asserted (ATVALID high), then the data was accepted this cycle from trace
source 1.
ATDATA1S[7:0] Input Trace data input from source 1.
ATID1S[6:0] Input Trace source ID for source 1. This must not change dynamically.
ATVAL ID 2S Input Data from trace source 2 is valid in this cycle.
ATREADY2 Output If this signal is asserted (ATVALI D high), then the data was accepted this cycle from trace
source 2.
ATDATA2S[7:0] Input Trace data input from source 2.
ATID2S[6:0] Input Trace source ID for source 2. This must not change dynamically.
Table 17-3 Miscellaneous configuration inputs
Name Type Description
MAXPORTSIZE[1:0] Input Defines the maximum number of pins available for synchronous trace output.
SyncReq Input Global trace synchronization trigger. Inserts synchronization packets into the
formatted data stream. Only used when the formatter is active. This signal must be
connected to the DSYNC output from Cortex-M3.
TRIGGER Input Causes a trigger packet to be inserted into the trace stream when the formatter is
active.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit