ARM Cortex-M3 User Manual

System Control
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 3-5
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3.1.2 Core debug registers
Table 3-2 gives a summary of the core debug registers. For a detailed description of the
core debug registers, see Chapter 10 Core Debug.
ISAR4: ISA Feature register4 Read-only 0xE000ED70 0x01310102
Software Trigger Interrupt Register Write Only 0xE000EF00 -
Peripheral identification register (PID4) Read-only
0xE000EFD0 0x04
Peripheral identification register (PID5) Read-only 0xE000EFD4 0x00
Peripheral identification register (PID6) Read-only 0xE000EFD8 0x00
Peripheral identification register (PID7) Read-only 0xE000EFDC 0x00
Peripheral identification register Bits [7:0] (PID0) Read-only 0xE000EFE0 0x00
Peripheral identification register Bits [15:8] (PID1) Read-only 0xE000EFE4 0xB0
Peripheral identification register Bits [23:16] (PID2) Read-only 0xE000EFE8 0x2B
Peripheral identification register Bits [31:24] (PID3) Read-only 0xE000EFEC 0x00
Component identification register Bits [7:0] (CID0) Read Only 0xE000EFF0 0x0D
Component identification register Bits [15:8] (CID1) Read-only 0xE000EFF4 0xE0
Component identification register Bits [23:16] (CID2) Read-only 0xE000EFF8 0x05
Component identification register Bits [31:24] (CID3) Read-only 0xE000EFFC 0xB1
a. Reset value depends on the number of interrupts defined.
Table 3-1 NVIC registers (continued)
Name of register Type Address Reset value
Table 3-2 Core debug registers
Name of register Type Address Reset Value
Debug Halting Control and Status Register Read/Write
0xE000EDF0
0x00000000
a
Debug Core Register Selector Register Write-only 0xE000EDF4 -
Debug Core Register Data Register Read/Write
0xE000EDF8 -
Debug Exception and Monitor Control Register. Read/Write
0xE000EDFC
0x00000000
b

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit