Core Debug
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 10-7
Unrestricted Access Non-Confidential
Table 10-3 shows the bit functions of the Debug Core Selector Register.
This write-only register generates a handshake to the core to transfer data to or from
Debug Core Register Data Register and the selected register. Until this core transaction
is complete, bit [16], S_REGRDY, of the DHCSR is 0.
Note
• Writes to this register in any size but word are Unpredictable.
• PSR registers are fully accessible this way, whereas some read as 0 when using
MRS instructions.
• All bits can be written, but some combinations cause a fault when execution is
resumed.
• IT might be written and behaves as though in an IT block.
Table 10-3 Debug Core Register Selector Register
Bits Type Field Function
[31:17] - - Reserved
[16] Write REGWnR Write = 1
Read = 0
[15:5] - - Reserved.
[4:0] Write REGSEL 5b00000 = R0
5b00001 = R1
…
5b01111 = DebugReturnAddress()
5b10000 = xPSR/Flags, execution state information, and exception
number
5b10001 = MSP (Main SP)
5b10010 = PSP (Process SP)
5b10100:
• CONTROL bits [31:24]
• FAULTMASK bits [23:16]
• BASEPRI bits [15:8]
• PRIMASK bits [7:0]
All unused values reserved
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