ARM Cortex-M3 User Manual

Embedded Trace Macrocell Interface
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 15-11
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Figure 15-7 Unconditional branch in execute aligned
Figure 15-8 Unconditional branch in execute unaligned
Table 15-4 shows an example of an opcode sequence.
ETMIVALID
ETMCCFAIL
ETMIA
BRCHSTAT
HTRANSI
HADDRI
HCLK
0x1000
0101 0000
NONSEQ
0x1008
0x1002 0x4000
NONSEQ NONSEQ NONSEQ
0x4000 0x4004 0x400C
NONSEQ
0x4008
ETMIVALID
ETMCCFAIL
ETMIA
BRCHSTAT
HTRANSI
HADDRI
HCLK
0x1000
0101 0000
NONSEQ
0x1002 0x4002
NONSEQ NONSEQ NONSEQ
0x4000 0x4004 0x4010 0x1008
NONSEQ NONSEQ
0x4008 0x400C
Table 15-4 Example of an opcode sequence
Execute cycle Fetch address Opcode
1
0x1020 ADD r1,#1
2 0x1022 LDR r3,[r4]
3 0x1024 ADD r2,#3
4 0x1026 CMP r3,r2
5 0x1028 BEQ = Target1
6 0x1040 CMP r1,r2
7 0x1042 ITE EQ // folded
8
0x1044 LDR EQ r3,[r4,r1] // skipped

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit