ARM Cortex-M3 User Manual

Embedded Trace Macrocell Interface
15-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Figure 15-9 on page 15-13 shows the timing sequence for the example opcode sequence
in Table 15-4 on page 15-11.
9 0x1046 LDR NE r3,[r4,r2]
10 0x1048 ADD r6,r3
11 0x104A NOP
12 0x104C BX r14
13 0x0FC4 CMP
14 0x0FC6 BEQ = Target2 // not taken
15 0x0FC8 BX r5
Table 15-4 Example of an opcode sequence (continued)
Execute cycle Fetch address Opcode

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit