ARM Cortex-M3 User Manual

Exceptions
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5.2 Exception types
Various types of exceptions exist in the processor. A fault is an exception that results
from an error condition because of instruction execution. Faults can be reported
synchronously or asynchronously to the instruction that caused them. In general, faults
are reported synchronously. The Imprecise Bus Fault is an asynchronous fault
supported in the ARMv7-M profile. A synchronous fault is always reported with the
instruction that caused the fault. An asynchronous fault does not guarantee how it is
reported with respect to the instruction that caused the fault.
For more information on exceptions, see the ARMv7-M Architecture Reference Manual.
Table 5-1 shows the exception type, position, and priority. Position refers to the word
offset from the start of the vector table. The lower numbers shown in the Priority column
of the table are higher priority. How the types are activated, synchronously or
asynchronously, is also shown. The exact meaning and use of priorities is explained in
Exception priority on page 5-6.
Table 5-1 Exception types
Exception type Position Priority Description
- 0 - Stack top is loaded from first entry of vector table on reset.
Reset 1 –3 (highest) Invoked on power up and warm reset. On first instruction,
drops to lowest priority (Thread mode). This is
asynchronous.
Non-maskable Interrupt 2 –2 Cannot be stopped or pre-empted by any exception but
reset. This is asynchronous.
Hard Fault 3 –1 All classes of Fault, when the fault cannot activate because
of priority or the Configurable Fault handler has been
disabled. This is synchronous.
Memory Management 4
Configurable
a
Memory Protection Unit (MPU) mismatch, including
access violation and no match. This is synchronous. This is
used even if the MPU is disabled or not present, to support
the Executable Never (XN) regions of the default memory
map.
Bus Fault 5
Configurable
a
Pre-fetch fault, memory access fault, and other
address/memory related. This is synchronous when precise
and asynchronous when imprecise.
Usage Fault 6
Configurable
a
Usage fault, such as Undefined instruction executed or
illegal state transition attempt. This is synchronous.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit