ARM Cortex-M3 User Manual

System Debug
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-37
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Figure 11-17 on page 11-37 shows the ITM Integration Mode Control Register bit
assignments.
Figure 11-17 ITM Integration Mode Control bit assignments
Table 11-25 describes the bit assignments of the ITM Integration Mode Control
Register
ITM Lock Access Register
Use this register to prevent write accesses to the Control Register.
Table 11-26 describes the bit assignments of the ITM Lock Access Register
ITM Lock Status Register
Use this register to enable write accesses to the Control Register.
Figure 11-18 on page 11-38 shows the ITM Lock Status Register bit assignments.
31
0
1
Reserved
INTEGRATION
Table 11-25 ITM Integration Mode Control Register bit assignments
Bits Field Function
[31:1] - Reserved
[0] INTEGRATION 0 = ATVALIDM normal
1 = ATVALIDM driven from Integration Write Register
Table 11-26 ITM Lock Access Register bit assignments
Bits Field Function
[31:0] Lock Access A privileged write of
0xC5ACCE55 enables more write access to Control Register 0xE00::0xFFC . An
invalid write removes write access.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit