ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-17
Unrestricted Access Non-Confidential
Interrupt Priority Registers
Use the Interrupt Priority Registers to assign a priority from 0 to 255 to each of the
available interrupts. 0 is the highest priority, and 255 is the lowest.
The priority registers are stored with the implemented values first. This means that if
there are four bits of priority, the priority value is stored in bits [7:4] of the byte.
However, if there are three bits of priority, the priority value is stored in bits [7:5] of the
byte. This means that an application can work even if it does not know how many
priorities are possible.
The register address, access type, and Reset state are:
Address
0xE000E400 - 0xE000E41F
Access Read/write
Reset state
0x00000000
Figure 8-7 shows the bit assignments of Interrupt Priority Registers 0-7 for interrupts
0-31.
Figure 8-7 Interrupt Priority Registers 0-31 bit assignments
The lower PRI_n bits can specify subpriorities for priority grouping. See Exception
priority on page 5-6.
31 23 15 7 0
PRI_3 PRI_2 PRI_1 PRI_0
PRI_7 PRI_6 PRI_5 PRI_4
PRI_11 PRI_10 PRI_9 PRI_8
PRI_15 PRI_14 PRI_13 PRI_12
PRI_19 PRI_18 PRI_17 PRI_16
PRI_23 PRI_22 PRI_21 PRI_20
PRI_27 PRI_26 PRI_25 PRI_24
PRI_31 PRI_30 PRI_29 PRI_28
81624
E000E400
E000E404
E000E408
E000E40C
E000E410
E000E414
E000E418
E000E41C

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit