ARM Cortex-M3 User Manual

AHB Trace Macrocell Interface
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 16-3
Unrestricted Access Non-Confidential
16.2 CPU AHB trace macrocell interface port descriptions
Table 16-1 list the AHB interface ports.
Table 16-1 AHB interface ports
Port name Direction Description
HTMDHADDR[31:0] Output 32-bit address.
HTMDHTRANS[1:0] Output Output indicates the type of the current data transfer. Can be IDLE,
NONSEQUENTIAL, OR SEQUENTIAL.
HTMDHSIZE[1:0] Output Indicates the size of the access. Can be 8, 16, or 32 bits.
HTMDHBURST[2:0] Output Output indicates if the transfer is part of a burst.
HTMDHPROT[3:0] Output Provides information on the access.
HTMDHWDATA[31:0] Output 32-bit write data bus.
HTMDHWRITE Output Write not read.
HTMDHRDATA[31:0] Output Read data bus.
HTMDHREADY Output When HIGH indicates that a transfer has completed on the bus. The signal is
driven LOW to extend a transfer.
HTMDHRESP[1:0] Output The transfer response status. OKAY or ERROR.
HTMDHADDR[31:0] Output 32-bit address.
HTMDHTRANS[1:0] Output Output indicates the type of the current data transfer. Can be IDLE,
NONSEQUENTIAL, OR SEQUENTIAL.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit