ARM Cortex-M3 User Manual

Introduction
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1.6 Store buffers
The processor contains two store buffers:
• Cortex-M3 core LSU store buffer for immediate offset opcode.
• Bus-matrix store buffer for wait states and unaligned transactions.
The core store buffer optimizes the case of
STR rx,[ry,#imm], which is common in
compiled code. This means that the next opcode can overlap the store's data phase,
reducing the opcode to a single cycle from the perspective of the pipeline.
The bus-matrix interconnect within the processor manages the unaligned behavior of
the core and bit-banding. The bus-matrix store buffer is useful for resolving system
wait-states and unaligned accesses that are split over multiple transactions.
Only transactions marked as bufferable use the store buffers. Stacking operations are
inherently non-bufferable and therefore also do not use either of the buffers.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit