ARM Cortex-M3 User Manual

AC Characteristics
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 19-9
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Table 19-14 shows the timing parameters for the ETM interface output ports.
Table 19-15 shows the timing parameters for the AHB Trace Macrocell (HTM) interface
output ports.
Table 19-14 ETM interface output ports timing parameters
Output delay Min. Output delay Max. Signal name
Clock uncertainty 30% ETMTRIGGER[3:0]
Clock uncertainty 30% ETMTRIGINOTD[3:0]
Clock uncertainty 30% ETMIVALID
Clock uncertainty 30% ETMDVALID
Clock uncertainty 30% ETMFOLD
Clock uncertainty 30% ETMCANCEL
Clock uncertainty 30% ETMIA[31:1]
Clock uncertainty 30% ETMICCFAIL
Clock uncertainty 30% ETMIBRANCH
Clock uncertainty 30% ETMIINDBR
Clock uncertainty 30% ETMFLUSH
Clock uncertainty 30% ETMFINDBR
Clock uncertainty 30% ETMINTSTAT[2:0]
Clock uncertainty 30% ETMINTNUM[8:0]
Clock uncertainty 30% ETMISTALL
Clock uncertainty 30% DSYNC
Table 19-15 HTM interface output ports timing parameters
Output delay Min. Output delay Max. Signal name
Clock uncertainty 50% HTMDHADDR[31:0]
Clock uncertainty 50% HTMDHTRANS[1:0]
Clock uncertainty 50% HTMDHSIZE[2:0]

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit