ARM Cortex-M3 User Manual

Nested Vectored Interrupt Controller
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-3
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8.2 NVIC programmer’s model
This section lists and describes the NVIC registers. It contains the following:
• NVIC register map
• NVIC register descriptions on page 8-7.
8.2.1 NVIC register map
Table 8-1 lists the NVIC registers. The System Control space includes the NVIC. The
NVIC space is split as follows:
•
0xE000E000 - 0xE000E00F . Interrupt Type Register
•
0xE000E010 - 0xE000E0FF . System Timer
•
0xE000E100 - 0xE000ECFF . NVIC
•
0xE000ED00 - 0xE000ED8F . System Control Block, including:
—CPUID
— System control, configuration, and status
— Fault reporting
•
0xE000EF00 - 0xE000EF0F . Software Trigger Exception Register
•
0xE000EFD0 - 0xE000EFFF. ID space.
Table 8-1 NVIC registers
Name of register Type Address
Reset
value
Page
Interrupt Control Type Register Read-only
0xE000E004
a
page 8-7
Auxiliary Control Register Read/write 0xE000E008 0x00000000 page 8-8
SysTick Control and Status Register Read/write
0xE000E010 0x00000000 page 8-9
SysTick Reload Value Register Read/write
0xE000E014 Unpredictable page 8-10
SysTick Current Value Register Read/write clear
0xE000E018 Unpredictable page 8-11
SysTick Calibration Value Register Read-only
0xE000E01C STCALIB page 8-12
Irq 0 to 31 Set Enable Register Read/write
0xE000E100 0x00000000 page 8-13
.....
.....
.....
Irq 224 to 239 Set Enable Register Read/write
0xE000E11C 0x00000000 page 8-13

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit