To Next Page

To Previous Page

Nested Vectored Interrupt Controller

Non-Confidential

Unrestricted Access

Irq 0 to 31 Clear Enable Register Read/write

0xE000E180 0x00000000

page 8-14

.....

Irq 224 to 239 Clear Enable Register Read/write

0xE000E19C 0x00000000

page 8-14

Irq 0 to 31 Set Pending Register Read/write

0xE000E200 0x00000000

page 8-15

.....

Irq 224 to 239 Set Pending Register Read/write

0xE000E21C 0x00000000

page 8-15

Irq 0 to 31 Clear Pending Register Read/write

0xE000E280 0x00000000

page 8-15

.....

Irq 224 to 239 Clear Pending Register Read/write

0xE000E29C 0x00000000

page 8-15

Irq 0 to 31 Active Bit Register Read-only

0xE000E300 0x00000000

page 8-16

.....

Irq 224 to 239 Active Bit Register Read-only

0xE000E31C 0x00000000

page 8-16

Irq 0 to 3 Priority Register Read/write

0xE000E400 0x00000000

page 8-17

.....

Table 8-1 NVIC registers (continued)

Name of register Type Address

Reset

value

Page

Questions and Answers:

Need help?

Do you have a question about the ARM Cortex-M3 and is the answer not in the manual?

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit