ARM Cortex-M3

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Nested Vectored Interrupt Controller

8-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G

Non-Confidential

Unrestricted Access

Irq 0 to 31 Clear Enable Register Read/write

0xE000E180 0x00000000

page 8-14

.....

.....

.....

Irq 224 to 239 Clear Enable Register Read/write

0xE000E19C 0x00000000

page 8-14

Irq 0 to 31 Set Pending Register Read/write

0xE000E200 0x00000000

page 8-15

.....

.....

.....

Irq 224 to 239 Set Pending Register Read/write

0xE000E21C 0x00000000

page 8-15

Irq 0 to 31 Clear Pending Register Read/write

0xE000E280 0x00000000

page 8-15

.....

.....

.....

Irq 224 to 239 Clear Pending Register Read/write

0xE000E29C 0x00000000

page 8-15

Irq 0 to 31 Active Bit Register Read-only

0xE000E300 0x00000000

page 8-16

.....

.....

.....

Irq 224 to 239 Active Bit Register Read-only

0xE000E31C 0x00000000

page 8-16

Irq 0 to 3 Priority Register Read/write

0xE000E400 0x00000000

page 8-17

.....

.....

.....

Table 8-1 NVIC registers (continued)

Name of register Type Address

Reset

value

Page

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