ARM Cortex-M3 User Manual

Exceptions
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5.14 Flowcharts
This section summarizes interrupt flow with:
• Interrupt handling
• Pre-emption on page 5-35
• Return on page 5-35.
5.14.1 Interrupt handling
Figure 5-6 shows how instructions execute until pre-empted by a higher-priority
interrupt.
Figure 5-6 Interrupt handling flowchart
Execute instruction
No
Yes
Yes
Return from
interrupt
No
Pending interrupt
higher priority than
active interrupt?
Reset
Load SP and PC from
locations 0, 4
Yes
Pre-empt
PC at return location?
No
Pending interrupt
higher priority than
stacked interrupt ?

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit