ARM Cortex-M3 User Manual

System Debug
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 11-33
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Note
Privileged writes are accepted to this register if ITMENA is set. User writes are
accepted to this register if ITMENA is set and the appropriate privilege mask is cleared.
Privileged access to the stimulus ports enables an RTOS kernel to guarantee
instrumentation slots or bandwidth as required.
ITM Trace Privilege Register
Use the ITM Trace Privilege Register to enable an operating system to control which
stimulus ports are accessible by user code.
Note
You can only write to this register in privileged mode.
The register address, access type, and Reset state are:
Access Read/write
Address
0xE0000E40
Reset 0x00000000
Figure 11-13 shows the ITM Trace Privilege Register bit assignments.
Figure 11-13 ITM Trace Privilege Register bit assignments
Table 11-21 describes the bit assignments of the ITM Trace Privilege Register.
Reserved
31 43 0
PRIVMASK
Table 11-21 ITM Trace Privilege Register bit assignments
Bits Field Function
[31:4] - Reserved.
[3:0] PRIVMASK Bit mask to enable tracing on ITM stimulus ports:
bit [0] = stimulus ports [7:0]
bit [1] = stimulus ports [15:8]
bit [2] = stimulus ports [23:16]
bit [3] = stimulus ports [31:24].

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit