ARM Cortex-M3 User Manual

Embedded Trace Macrocell
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 14-3
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Figure 14-1 ETM block diagram
14.1.2 ETM inputs and outputs
This section describes the ETM inputs and outputs:
• ETM core interface. See Table 14-1 on page 14-4.
• Miscellaneous configuration inputs. See Table 14-2 on page 14-4.
• Trace port signals. See Table 14-2 on page 14-4.
• Other signals. See Table 14-4 on page 14-5.
• Clocks and resets. See Table 14-5 on page 14-6.
CM3Trigger
CM3
EtmResCntrl
CM3
EtmTrigEvt
CM3
EtmTrcEn
CM3Trace
CM3Etm
Control
CM3Etm
FifoPeek
CM3Etm
Fifo
CM3Etm
APBIf
CM3Etm
TraceOut
CPU I/F
APB I/F
CM3ETM
TPIU
Formatter
TPIU
FIFO
TPIU
Output
Stage
TRACEDATA [3:0
]
TRACECLK
SWV
ATB
from
ITM
TRACECLKIN
CM3 TPIU
Triggers

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit